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1 ? HI5762 dual 10-bit, 60msps a/d converter with internal voltage reference the HI5762 is a monolithic, dual 10-bit, 60msps analog-to-digital converter fabricated in an advanced cmos process. it is designed for high speed applications where integration, bandwidth and accuracy are essential. built by combining two cores of the hi5767 single channel 10-bit 60msps analog-to-digital converter, the HI5762 reaches a new level of multi-channel integration. the fully pipeline architecture and an innovative input stage enable the HI5762 to accept a variety of input configurations, single- ended or fully differential. only one external clock is necessary to drive both converters and an internal band-gap voltage reference is provid ed. this allows the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. the HI5762 has excellent dynamic performance while consuming only 650mw of pow er at 60msps. the a/d only requires a single +5v power supply and encode clock. data output latches are provided wh ich present valid data to the output bus with a latency of 6 clock cycles. for those customers needing dual channel 8-bit resolution, please refer to the hi5662. for single channel 10-bit applications, please refer to the hi5767. features ? sampling rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 60msps ? 8.8 bits at f in = 10mhz ? low power at 60msps . . . . . . . . . . . . . . . . . . . . 650mw ? wide full power input bandwidth . . . . . . . . . . . . 250mhz ? excellent channel-to-channel isolation . . . . . . . . . .>75db ? on-chip sample and hold amplifiers ? internal band-gap voltage reference . . . . . . . . . . . . 2.5v ? fully differential or single-ended analog inputs ? single supply voltage operation . . . . . . . . . . . . . . . . .+5v ? ttl/cmos compatible sampling clock input ? cmos compatible digital outputs. . . . . . . . . . . 3.0v/5.0v ? offset binary digital data output format ? dual 10-bit a/d converters on a monolithic chip applications ? wireless local loop ? psk and qam i&q demodulators ? medical imaging ? high speed data acquisition ordering information part number part marking temp. range (c) package pkg. dwg. # HI5762/6in HI5762/6in -40 to +85 44 ld mqfp q44.10x10 HI5762/6inz (notes 1, 2) HI5762 /6inz -40 to +85 44 ld mqfp (pb-free) q44.10x10 HI5762eval2 25 evaluation platform notes: 1. these intersil pb-free plastic packaged products employ special pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal ( e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-f ree products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. for moisture sensitivity level (msl), please see device information page for HI5762 . for more information on msl please see techbrief tb363 . data sheet january 22, 2010 fn4318.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 1999, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn4318.3 january 22, 2010 pinout HI5762 (44 ld mqfp) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 a gnd av cc2 id8 id7 id6 id5 dv cc3 d gnd id4 id3 id9 a gnd av cc2 qd8 qd7 qd6 qd5 dv cc3 d gnd qd4 qd3 qd9 id2 id1 id0 d gnd dv cc1 clk dv cc2 d gnd qd0 qd1 qd2 iv dc i in- i in+ a gnd v rin nc v rout av cc1 q in+ q in- qv dc HI5762
3 fn4318.3 january 22, 2010 functional block diagram dv cc3 + - stage 1 stage 8 clock bias i/qv dc i/q in - i/q in + i/qd0 (lsb) i/qd1 i/qd2 i/qd3 i/qd4 i/qd5 i/qd6 i/qd7 i/qd8 i/qd9 (msb) clk av cc1,2 agnd dv cc1,2 dgnd stage 9 x2 s/h 2-bit flash 2-bit dac + - x2 2-bit flash 2-bit dac 2-bit flash digital delay and digital error correction reference v refout v refin i or q channel HI5762
4 fn4318.3 january 22, 2010 typical application schematic are placed as close 10 f and 0.1 f caps qd9 qd8 qd7 qd6 qd5 qd4 qd3 qd2 qd1 qd0 bnc clock 10 f 0.1 f10 f + + dgnd agnd (38) v rout (40) v rin clk (17) dgnd (9,15,19,25) (1,33,41) agnd (lsb) qd0 (20) qd1 (21) qd2 (22) qd3 (23) qd4 (24) qd5 (27) qd6 (28) qd7 (29) qd8 (30) (msb) qd9 (31) (2,32) av cc2 (37) av cc1 dv cc1 (16) to part as possible 0.1 f +5v +5v 0.1 f id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 (lsb) id0 (14) id1 (13) id2 (12) id3 (11) id4 (10) id5 (7) id6 (6) id7 (5) id8 (4) (msb) id9 (3) i in + i in - (43) i in - (42) i in + (44) iv dc 0.1 f10 f + dv cc3 (8,26) +5v or +3v dv cc2 (18) (39) nc q in + q in - (35) q in - (36) q in + (34) qv dc HI5762 HI5762
5 fn4318.3 january 22, 2010 pin descriptions pin no. name description 1a gnd analog ground 2av cc2 analog supply (+5.0v) 3 id9 i-channel, data bit 9 output (msb) 4 id8 i-channel, data bit 8 output 5 id7 i-channel, data bit 7 output 6 id6 i-channel data bit 6 output 7 id5 i-channel, data bit 5 output 8dv cc3 digital output supply (+3.0v or +5.0v) 9d gnd digital ground 10 id4 i-channel, data bit 4 output 11 id3 i-channel, data bit 3 output 12 id2 i-channel, data bit 2 output 13 id1 i-channel, data bit 1 output 14 id0 i-channel, data bit 0 output (lsb) 15 d gnd digital ground 16 dv cc1 digital supply (+5.0v) 17 clk sample clock input 18 dv cc2 digital supply (+5.0v) 19 d gnd digital ground 20 qd0 q-channel, data bit 0 output (lsb) 21 qd1 q-channel, data bit 1 output 22 qd2 q-channel, data bit 2 output 23 qd3 q-channel, data bit 3 output 24 qd4 q-channel, data bit 4 output 25 dgnd digital ground 26 dv cc3 digital output supply (+3.0v or +5.0v) 27 qd5 q-channel, data bit 5 output 28 qd6 q-channel, data bit 6 output 29 qd7 q-channel, data bit 7 output 30 qd8 q-channel, data bit 8 output 31 qd9 q-channel, data bit 9 output (msb) 32 av cc2 analog supply (+5.0v) 33 a gnd analog ground 34 qv dc q-channel dc bias voltage output 35 q in- q-channel negative analog input 36 q in+ q-channel positive analog input 37 av cc1 analog supply (+5.0v) 38 v rout +2.5v reference voltage output 39 nc no connect 40 v rin +2.5v reference voltage input 41 a gnd analog ground 42 i in+ i-channel positive analog input 43 i in- i-channel negative analog input 44 iv dc i-channel dc bias voltage output pin no. name description HI5762
6 fn4318.3 january 22, 2010 absolute m aximum ratings t a = +25c thermal information supply voltage, av cc or dv cc to agnd or dgnd . . . . . . . . . . .6v dgnd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v digital i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd to dv cc analog i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd to av cc operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, note 3) ja (c/w) 44 ld mqfp package . . . . . . . . . . . . . . . . . . . . . . . 75 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . -65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications av cc1,2 = dv cc1,2 = +5.0v, dv cc3 = +3.0v; v rin = 2.50v; f s = 60msps at 50% duty cycle; c l = 10pf; t a = +25c; differential analog input ; unless otherwise specified parameter test conditions min typ max units accuracy resolution 10 - - bits integral linearity error, inl f in = 10mhz - 2 - lsb differential linearity error, dnl (guaranteed no missing codes) f in = 10mhz - 0.4 1.0 lsb offset error, v os f in = dc -40 - +40 lsb full scale error, fse f in = dc - 4 - lsb dynamic characteristics minimum conversion rate no missing codes - 1 - msps maximum conversion rate no missing codes 60 - - msps effective number of bits, enob f in = 10mhz 8.4 8.8 - bits signal to noise and distortion ratio, sinad f in = 10mhz - 54.7 - db signal to noise ratio, snr f in = 10mhz - 54.7 - db total harmonic distortion, thd f in = 10mhz - -68 - dbc 2nd harmonic distortion f in = 10mhz - -70 - dbc 3rd harmonic distortion f in = 10mhz - -73 - dbc spurious free dynamic range, sfdr f in = 10mhz - 70 - dbc intermodulation distortion, imd f 1 = 1mhz, f 2 = 1.02mhz - 64 - dbc i/q channel crosstalk --75- dbc i/q channel offset match -10- lsb i/q channel full scale error match - 10 - lsb transient response (note 4) - 1 - cycle overvoltage recovery 0.2v overdrive (note 4) - 1 - cycle analog input maximum peak-to-peak differential analog input range (v in + - v in -) - 0.5 - v maximum peak-to-peak single-ended analog input range -1.0- v analog input resistance, r in+ or r in- v in+ , v in- = v ref , dc - 1 - m rms signal rms noise + distortion -------------------------------------------------------------- = rms signal rms noise ------------------------------- = HI5762
7 fn4318.3 january 22, 2010 analog input capacitance, c in+ or c in- v in+ , v in- = 2.5v, dc - 10 - pf analog input bias current, i b + or i b -v in+ , v in- = v ref- , v ref+ ,dc (note 4, 5) -10 - 10 a differential analog input bias current i bdiff = (i b + - i b -) (notes 4, 5) -0.5 - +0.5 a full power input bandwidth, fpbw (note 4) - 250 - mhz analog input common mode voltage range (v in + + v in -)/2 differential mode (note 4) 0.25 - 4.75 v internal voltage reference reference output voltage, v rout (loaded) 2.35 2.5 2.65 v reference output current, i rout -24ma reference temperature coefficient - -400 - ppm/ o c reference voltage input reference voltage input, v rin -2.5- v total reference resistance, r rin with v rin = 2.5v - 1.25 - k reference current, i rin with v rin = 2.5v - 2 - ma dc bias voltage dc bias voltage output, v dc -3.0- v maximum output current --0.4ma sampling clock input input logic high voltage, v ih clk 2.0 - - v input logic low voltage, v il clk - - 0.8 v input logic high current, i ih clk, v ih = 5v -10.0 - +10.0 a input logic low current, i il clk, v il = 0v -10.0 - +10.0 a input capacitance, c in clk - 7 - pf digital outputs output logic high voltage, v oh i oh = 100a; dv cc3 = 5v 4.0 - - v output logic low voltage, v ol i ol = 100a; dv cc3 = 5v - - 0.8 v output logic high voltage, v oh i oh = 100a; dv cc3 = 3v 2.4 - - v output logic low voltage, v ol i ol = 100a; dv cc3 = 3v - - 0.5 v output capacitance, c out -7- pf timing characteristics aperture delay, t ap -5- ns aperture jitter, t aj -5-ps rms data output hold, t h - 10.7 - ns data output delay, t od - 11.7 - ns data latency, t lat for a valid sample (note 4) 6 6 6 cycles power-up initialization data invalid time (note 4) - - 20 cycles sample clock pulse width (low) (note 4) 7.5 8.3 - ns sample clock pulse width (high) (note 4) 7.5 8.3 - ns sample clock duty cycle variation - 5- % power supply characteristics analog supply voltage, av cc (note 4) 4.75 5.0 5.25 v electrical specifications av cc1,2 = dv cc1,2 = +5.0v, dv cc3 = +3.0v; v rin = 2.50v; f s = 60msps at 50% duty cycle; c l = 10pf; t a = +25c; differential analog i nput; unless otherwise specified (continued) parameter test conditions min typ max units HI5762
8 fn4318.3 january 22, 2010 digital supply voltage, dv cc1 and dv cc2 (note 4) 4.75 5.0 5.25 v digital output supply voltage, dv cc3 at 3.0v (note 4) 2.7 3.0 3.3 v at 5.0v (note 4) 4.75 5.0 5.25 v supply current, i cc f s = 60msps - 130 - ma power dissipation - 650 670 mw offset error sensitivity, v os av cc or dv cc = 5v 5% - 0.5 - lsb gain error sensitivity, fse av cc or dv cc = 5v 5% - 0.6 - lsb notes: 4. limits established by characteri zation and are not production tested. 5. with the clock low and dc input. electrical specifications av cc1,2 = dv cc1,2 = +5.0v, dv cc3 = +3.0v; v rin = 2.50v; f s = 60msps at 50% duty cycle; c l = 10pf; t a = +25c; differential analog i nput; unless otherwise specified (continued) parameter test conditions min typ max units timing waveforms notes: 6. s n : n-th sampling period. 7. h n : n-th holding period. 8. b m , n : m-th stage digital output corresponding to n-th sampled input. 9. d n : final data output corresponding to n-th sampled input. figure 1. HI5762 internal circuit timing d n - 6 d n - 5 d n - 1 d n d n + 1 d n + 2 analog input clock input input s/h 1st stage 2nd stage 9th stage data output s n - 1 h n - 1 s n h n s n + 1 h n + 1 s n + 2 s n + 5 h n + 5 s n + 6 h n + 6 s n + 7 h n + 7 s n + 8 h n + 8 b 1 , n - 1 b 1 , n b 1 , n + 1 b 1 , n + 4 b 1 , n + 5 b 1 , n + 6 b 1 , n + 7 b 2 , n - 2 b 2 , n - 1 b 2 , n b 2 , n + 4 b 2 , n + 5 b 2 , n + 6 b 9 , n - 5 b 9 , n - 4 b 9 , n b 9 , n + 1 b 9 , n + 2 b 9 , n + 3 t lat HI5762
9 fn4318.3 january 22, 2010 figure 2. HI5762 input-to output timing timing waveforms (continued) t od t h data n-1 data n clock input data output 1.5v t ap analog input t aj 1.5v 2.4v 0.5v typical performance curves figure 3. effective number of bits (enob) and sinad vs input frequency figure 4. snr vs input frequency figure 5. -thd, -2hd and -3hd vs input frequency figure 6. sinad, snr and -thd vs input amplitude enob (bits) sinad (db) 9 8 7 6 1m 10m 100m input frequency (hz) f s = 60msps t a = +25c 56 50 44 38 snr (db) 56 50 44 38 1m 10m 100m input frequency (mhz) f s = 60msps t a = +25c dbc 90 1m 10m 100m input frequency (hz) f s = 60msps t a = +25c 85 80 75 70 65 60 55 50 -3hd -2hd -thd db 70 -40 input level (dbfs) 60 50 40 30 -20 0 sinad (db) snr (db) -thd (dbc) 20 -30 -10 f s = 60msps f in = 10mhz t a = +25c HI5762
10 fn4318.3 january 22, 2010 figure 7. effective number of bits (enob) vs sample clock duty cycle figure 8. supply current vs sample clock frequency figure 9. effective number of bits (enob) vs temperature figure 10. internal reference voltage (v rout ) vs temperature figure 11. dc bias voltage (i/qv dc ) vs temperature figure 12. data output delay (t od ) vs temperature typical performance curves (continued) enob (bits) 9 40 duty cycle (%, t hi /t clk ) 42 44 46 48 50 52 54 56 58 60 5 6 7 8 f s = 60msps t a = +25c 1mhz < f in < 15mhz supply current (ma) 10 f s (msps) 20 30 50 60 70 0 t a = +25c 1mhz < f in < 15mhz 40 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 i cc ai cc di cc2 di cc1 di cc3 enob (bits) 9.0 temperature (c) 020406080 7.0 7.5 8.0 8.5 f s = 60msps f in = 10mhz i channel q channel -20 -40 internal reference voltage 2.50 temperature (c) 020406080 v rout -20 -40 2.49 2.48 2.47 2.46 2.45 2.44 2.43 2.42 2.41 2.40 v rout (v) dc bias voltage, i/qv dc (v) 3.10 temperature (c) 0 20406080 qv dc -20 -40 3.05 3.00 2.95 2.90 2.85 iv dc t od (ns) 13.0 temperature (c) 0 20406080 -20 -40 12.5 12.0 11.5 11.0 t od HI5762
11 fn4318.3 january 22, 2010 detailed description theory of operation the HI5762 is a dual 10-bit fully differential sampling pipeline a/d converter with digital error correction logic. figure 15 depicts the circuit for the front-end differential-in-differential- out sample-and-hold (s/h) amplifiers. the switches are controlled by an internal sampling clock which is a non-overlapping two phase signal , 1 and 2 , derived from the master sampling clock. during the sampling phase, 1 , the input signal is applied to the sampling capacitors, c s . at the same time the holding capacitors, c h , are discharged to analog ground. at the falling edge of 1 the input signal is sampled on the bottom plates of the sampling capacitors. in the next clock phase, 2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op amp output nodes. the charge then redistributes between c s and c h completing one sample-and-hold cycle. the front end sample-and-hold output is a fully-differential, sampled-data representation of the analog input. the circuit not only performs the sample-and- hold function but will also conv ert a single-ended input to a fully-differential output for the converter core. during the sampling phase, the i/q in pins see only the on-resistance of a switch and c s . the relatively small values of these components result in a typical full power input bandwidth of 250mhz for the converter. figure 13. supply current vs temperature figure 14. 2048 point fft plot typical performance curves (continued) supply current (ma) 0 140 120 100 80 60 40 20 temperature (c) 020406080 -20 -40 f s = 60msps 1mhz < f in < 15mhz ai cc i cc di cc1 di cc2 di cc3 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 100 200 300 400 500 600 700 800 900 1023 frequency (bin) db f s = 60msps f in = 10mhz t a = +25c table 1. a/d code table code center description differential input voltage (i/q in + - i/q in -) offset binary output code msb lsb i/qd9 i/qd8 i/qd7 i/qd6 i/qd5 i/qd4 i/qd3 i/qd2 i/qd1 i/qd0 +full scale (+fs) - 1 / 4 lsb 0.499756v 1 1 1 1 1 1 1 1 1 1 +fs - 1 1 / 4 lsb 0.498779v 1 1 1 1 1 1 1 1 1 0 + 3 / 4 lsb 732.422 v 1000000000 - 1 / 4 lsb -244.141 v 0111111111 -fs + 1 3 / 4 lsb -0.498291v 0 0 0 0 0 0 0 0 0 1 -full scale (-fs) + 3 / 4 lsb -0.499268v 0 0 0 0 0 0 0 0 0 0 note: 10. the voltages listed above represent the ideal center of each output code shown with v refin =+2.5v. - + + - c h c s c s c h i/q in+ v out+ v out- i/q in- 1 1 1 2 1 1 1 figure 15. analog input sample-and-hold HI5762
12 fn4318.3 january 22, 2010 as illustrated in the ?functional block diagram? on page 3 and the timing diagram in figure 1 on page 8, eight identical pipeline subconverter stages, each containing a two-bit flash converter and a two-bit multiplying digital-to-analog converter, follow the s/h circ uit with the ninth stage being a two bit flash converter. each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. each individual subconverter clock signal is offset by 180 from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. the output of each of the eight identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. the output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. the function of the digital delay line is to time align the digital outputs of the eight identical two-bit subconverte r stages with the corresponding output of the ninth stage flash converter before applying the eighteen bit result to the digital error correction logic. the digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final ten bit digital data output of the converter. because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus following the 6th cycle of the clock after the analog sample is taken (see the timing diagram in figure 1 on page 8). this time delay is specified as the data latency. after the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. the digital output data is provided in offset binary format (see table 1, a/d code table). internal reference voltage output, v refout the HI5762 is equipped with an internal reference voltage generator, therefore, no external reference voltage is required. v rout must be connected to v rin when using the internal reference voltage. an internal band-gap reference voltage followed by an amplifier/buffer generates the precision +2.5v reference voltage used by the converter. a band-gap reference circuit is used to generate a precision +1.2 5v internal reference voltage. this voltage is then amplified by a wide-band uncompensated operational amplifier connected in a gain-of-two configuration. an external, user-supplied, 0.1f capacitor connected from the v rout output pin to analog ground is used to set the dominant pole and to maintain the stability of the operational amplifier. reference voltage input, v refin the HI5762 is designed to accept a +2.5v reference voltage source at the v rin input pin. typical operation of the converter requires v rin to be set at +2.5v. the HI5762 is tested with v rin connected to v rout yielding a fully differential analog input voltage range of 0.5v. the user does have the option of supplying an external +2.5v reference voltage. as a result of the high input impedance presented at the v rin input pin, 1.25k typically, the external reference voltage being used is only required to source 2ma of reference input current. in the situation where an external reference voltage will be used an external 0.1f capacitor must be connected from the v rout output pin to analog ground in order to maintain the stability of the internal operational amplifier. in order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, v rin . analog input, differential connection the analog input of the HI5762 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. a fully differential connection (figure 16 and figure 17) will deliver the best performance from the converter. since the HI5762 is powered by a single +5v analog supply, the analog input is limited to be between ground and +5v. for the differential input connection this implies the analog input common mode voltage can range from 0.25v to 4.75v. the performance of the adc d oes not change significantly with the value of the analog input common mode voltage. a dc voltage source, i/qv dc , equal to 3.0v (typical), is made available to the user to help simplify circuit design when using an ac-coupled differential input. this low output impedance voltage source is not designed to be a reference but makes an excellent dc bias source and stays well within the analog input common mode voltage range over temperature. for the ac-coupled differential input (see figure 16) and with v rin connected to v rout , full scale is achieved when the v in and -v in input signals are 0.5v p-p , with -v in being 180 out-of-phase with v in . the converter will be at positive full scale when the i/q in + input is at v dc + 0.25v and the i/q in - input is at v dc - 0.25v (i/q in +-i/q in - = +0.5v). conversely, the converter will be at negative full scale when the i/q in + input is equal to v dc - 0.25v and i/q in - is at v dc + 0.25v (i/q in + - i/q in -=-0.5v). i/q in + i/qv dc i/q in - HI5762 v in -v in r r figure 16. ac-coupled differential input HI5762
13 fn4318.3 january 22, 2010 the analog input can be dc coupled (see figure 17) as long as the inputs are within the analog input common mode voltage range (0.25v vdc 4.75v). the resistors, r, in figure 17 are not absolutely necessary but may be used as load settin g resistors. a capacitor, c, connected from i/q in + to i/q in - will help filter any high frequency noise on the inputs, also improving performance. values around 20pf are sufficient and can be used on ac-coupled inputs as well. note, however, that the value of capacitor c chosen must take into account the highest frequency component of the analog input signal. analog input, single-ended connection the configuration shown in figure 18 may be used with a single-ended ac-coupled input. again, with v rin connected to v rout , if v in is a 1v p-p sinewave, then i/q in + is a 1.0v p-p sinewave riding on a positive voltage equal to vdc. the converter will be at positive full scale when i/q in + is at vdc + 0.5v (i/q in + - i/q in -=+0.5v) and will be at negative full scale when i/q in + is equal to vdc - 0.5v (i/q in +-i/q in - = -0.5v). sufficient headroom must be provided such that the input voltage never goes above +5v or below agnd. in this case, vdc could range between 0.5v and 4.5v without a significan t change in adc performance. the simplest way to produce vdc is to use the dc bias source, i/qv dc , output of the HI5762. the single ended analog input can be dc-coupled (see figure 19) as long as the i nput is within the analog input common mode voltage range. the resistor, r, in figure 19 is not absolutely necessary but may be used as a load setting resistor. a capacitor, c, connected from i/q in + to i/q in - will help filter any high frequency noise on the inputs, also improving performance. values around 20pf are sufficient and can be used on ac-coupled inputs as well. note, however, that the value of capacitor c chosen must take into account the highest frequency component of the analog input signal. a single-ended source may give better overall system performance if it is first converted to differential before driving the HI5762. sampling clock requirements the HI5762 sampling clock input provides a standard high-speed interface to external ttl/cmos logic families. in order to ensure rated perfo rmance of the HI5762, the duty cycle of the clock should be held at 50% 5%. it must also have low jitter and operate at standard ttl/cmos levels. performance of the HI5762 will only be guaranteed at conversion rates above 1msps (typ). this ensures proper performance of the internal dynamic circuits. similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1msps must be performed before valid data is available. supply and ground considerations the HI5762 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. the digital data outputs also have a separate supply pin, dv cc3 , which can be powered from a 3.0v or 5.0v supply. this allows the outputs to interface with 3.0v logic if so desired. the part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. for best performance, the supplies to the HI5762 should be driven by clean, linear regulated supplies. the board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. if the part is powered off a single supply then the analog supply can be isolated by a ferrite bead from the digital supply. refer to the application note ?using intersil high-speed a/d converters? (an9214) for additional considerations when using high-speed converters. i/q in + i/qv dc i/q in - HI5762 v in -v in r r c v dc v dc figure 17. dc coupled differential input i/q in + i/q in - HI5762 v in v dc r figure 18. ac coupled single-ended input i/q in + i/q in - HI5762 v dc r c v in v dc figure 19. dc coupled single ended input HI5762
14 fn4318.3 january 22, 2010 static performa nce definitions offset error (v os ) the midscale code transition should occur at a level 1 / 4 lsb above half-scale. offset is defined as the deviation of the actual code transition from this point. full-scale error (fse) the last code transition should occur for an analog input that is 3 / 4 lsb below positive full scale (+fs) with the offset error removed. full scale error is defined as the deviation of the actual code transition from this point. differential linearity error (dnl) dnl is the worst case deviation of a code width from the ideal value of 1lsb. integral linearity error (inl) inl is the worst case deviation of a code center from a best fit straight line calculated from the measured data. power supply sensitivity each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error (in lsbs) is noted. dynamic performance definitions fast fourier transform (fft) techniques are used to evaluate the dynamic perform ance of the HI5762. a low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in ram. the data is then transformed into the frequency domain with an fft and analyzed to evaluate the dynamic performance of the a/d. the sine wave input to the part is typically -0.5db down from full scale for all these tests. snr and sinad are quoted in db. the distortion numbers are quoted in dbc (decibels with respect to carrier) and do not include any correction factors for normalizing to full scale. the effective number of bits (enob) is calculated from the sinad data by equation 1: where: v corr = 0.5db (typ). v corr adjusts the sinad, and hence the enob, for the amount the analog input signal is backed off from full scale. signal to noise and distortion ratio (sinad) sinad is the ratio of the measured rms signal to rms sum of all the other spectral components below the nyquist frequency, f s /2, excluding dc. signal to noise ratio (snr) snr is the ratio of the measured rms signal to rms noise at a specified input and sampling frequency. the noise is the rms sum of all of the spectral components below f s /2 excluding the fundamental, the first five harmonics and dc. total harmonic distortion (thd) thd is the ratio of the rms sum of the first 5 harmonic components to the rms value of the fundamental input signal. 2nd and 3rd harmonic distortion this is the ratio of the rms value of the applicable harmonic component to the rms value of the fundamental input signal. spurious free dynamic range (sfdr) sfdr is the ratio of the fundamental rms amplitude to the rms amplitude of the next larges t spectral component in the spectrum below f s /2. intermodulation distortion (imd) nonlinearities in the signal path will tend to generate intermodulation products when two tones, f 1 and f 2 , are present at the inputs. the ratio of the measured signal to the distortion terms is calculated. the terms included in the calculation are (f 1 +f 2 ), (f 1 -f 2 ), (2f 1 ), (2f 2 ), (2f 1 +f 2 ), (2f 1 -f 2 ), (f 1 +2f 2 ), (f 1 -2f 2 ). the adc is tested with each tone 6db below full scale. transient response transient response is measured by providing a full-scale transition to the analog input of the adc and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. over-voltage recovery over-voltage recovery is measured by providing a full-scale transition to the analog input of the adc which overdrives the input by 200mv, and measur ing the number of cycles it takes for the output code to settle within 10-bit accuracy. full power input bandwidth (fpbw) full power input bandwidth is the analog input frequency at which the amplitude of the digi tally reconstructed output has decreased 3db below the amplit ude of the input sine wave. the input sine wave has an amplitude which swings from -fs to +fs. the bandwidth given is measured at the specified sampling frequency. enob sinad 1.76 ? v corr + () 6.02 ? = (eq. 1) HI5762
15 fn4318.3 january 22, 2010 i/q channel crosstalk i/q channel crosstalk is a measure of the amount of channel separation or isolation between the two a/d converter cores contained within the dual converter package. the measurement consists of stimulating one channel of the converter with a fullscale input signal and then measuring the am ount that signal is below, in dbc, a fullscale signal on the opposite channel. timing definitions refer to figure 1 and figure 2 for these definitions. aperture delay (t ap ) aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. this delay is due to internal clock path propagation delays. aperture jitter (t aj ) aperture jitter is the rms variation in the aperture delay due to variation of internal clock path delays. data hold time (t h ) data hold time is the time to where the previous data (n - 1) is no longer valid. data output delay time (t od ) data output delay time is the time to where the new data (n) is valid. data latency (t lat ) after the analog sample is taken, the digital data representing an analog input sample is output to the digital data bus following the 6th cycle of the clo ck after the analog sample is taken. this is due to the pipeline nature of the converter where the analog sample has to ripple through the internal subconverter stages. th is delay is specified as the data latency. after the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. the digital data lags the analog input sample by 6 sample clock cycles. power-up initialization this time is defined as the maximum number of clock cycles that are required to initialize the converter at power-up. the requirement arises from the ne ed to initialize the dynamic circuits within the converter. HI5762
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn4318.3 january 22, 2010 HI5762 metric plastic quad flatpack packages (mqfp) d d1 e e1 -a- pin 1 a2 a1 a 12 o -16 o 12 o -16 o 0 o -7 o 0.40 0.016 min l 0 o min plane b 0.005/0.009 0.13/0.23 with plating base metal seating 0.005/0.007 0.13/0.17 b1 -b- e 0.008 0.20 a-b s d s c m 0.076 0.003 -c- -d- -h- q44.10x10 (jedec ms-022ab issue b) 44 lead metric plastic quad flatpack package symbol inches millimeters notes min max min max a - 0.096 - 2.45 - a1 0.004 0.010 0.10 0.25 - a2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - d 0.515 0.524 13.08 13.32 3 d1 0.389 0.399 9.88 10.12 4, 5 e 0.516 0.523 13.10 13.30 3 e1 0.390 0.398 9.90 10.10 4, 5 l 0.029 0.040 0.73 1.03 - n44 447 e 0.032 bsc 0.80 bsc - rev. 2 4/99 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and toleranc es per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. ?n? is the number of terminal positions. -c- -h-

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